The adoption of through silicon vias has meant putting front-end wafer fab tools and processes in assembly and test houses.
For outsourced assembly and test (OSAT) houses either planning for or already offering through-silicon via (TSV) capability for their 3D packaging efforts, this has meant the front end is coming to the back end, in a manner of speaking.
A bit of an exaggeration perhaps, as most generalizations are. But thanks to TSVs, in a very real sense some of what would typically be the last steps involved in front-end wafer fab processes are also being implemented at OSATs, the traditional purveyors of back-end packaging, assembly and test.
Whether this expensive investment will pay off for them the long run remains to be seen.
As always, the questions are “When” and “If”
TSVs have proved a bit of a headache for the industry in general and OSATs in particular, as the technology — really several technologies or methodologies — has generated a lot of hype and consequently research in the last several years, but has yet to see widespread adoption. As always in the semiconductor industry, this has been because of a combination of factors: economics, chipmakers’ roadmaps and more expedient technical or economic solutions available in the near term, such as so-called 2.5D IC technology.
In fact, talk out of the recent Semicons—West and Taiwan—indicates there won’t be widespread industry adoption of TSVs in 3D ICs until about the 2016 time frame, or beyond the planar 20nm node.
Currently in terms of TSVs, the market largely comprises FPGAs using 2.5D technology, namely from Xilinx and Altera. There has been some use of vertically stacked memory to date, but only in the high-end server market, said Mark Stromberg, a principle research analyst at Gartner Inc.
Stacked memory may find its way into higher end communications products in 2014, but it will likely be 2015 or later before it could become widespread, Stromberg said. It won’t be until 2016 at the earliest that the chip industry could see TSVs used to connect multiple groups of stacked die in a single 3D package, such as processors, a graphics processor, memory and peripheral logic.
One of the reasons 2.5D has come into play in the FPGA space is the die sized involved: larger than 20mm on side; in high-end applications the economics consequently make sense, said Raj Pendse, vice president and chief marketing officer at STATS ChipPAC Ltd. In the coming years, when dies sizes get below 20mm, it’s possible the market will then see 3D ICs utilizing TSVs used in mobile applications processors.
“If it becomes real, beyond a critical-mass level, TSVs will continue beyond 16nm,” Pendse said. “This is providing a new dimension to scaling and Moore’s Law. That is a tremendous benefit,” largely in increased I/O bandwidth available, he said.
While TSVs are and could continue to prove a boon to makers of ICs for computing applications — FPGAs and ASICs — mobile device makers, and consequently consumer OEMs, have mixed feelings, Pendse said. They are naturally most concerned with what will enable them to stick to their various roadmaps in the most economical manner. Current alternatives in 3D-ICs and packaging, such as extending fan-out wafer level packaging, or future alternatives, such as new packaging substrates, may provide more cost-effective means of getting the device performance needed.
On the other hand, there seems to be little doubt in terms of consensus that 3D ICs are the wave of the immediate future. “At 15nm, if you’re not vertically integrating the silicon, you’re not going to get the device performance you need,” Stromberg said.
Old OSATs learning new tricks
While the widespread adoption of TSVs remains a question, the larger OSATs have nevertheless been making preparations for a more widespread adoption, climbing a steep and expensive learning curve. As Pendse observed, I/O densities required in advanced assemblies and packaging also require technologies that are outside the realm of traditional packaging.
TSVs connecting two die within a package through a thin passive interposer layer—so-called 2.5D tech—aren’t far from what advanced packaging houses have already been doing, he said. But exposing TSVs used to connect die stacked on top of each other—true 3D—involves something fairly new to the OSATs.
In general there are different methods and technologies for implementing TSVs. To put it simply, these vary with the application or chips involved—say, memory or logic—and the type of packaging that will ultimately be used. Whether it can or should be done in the fab or at the OSAT depends on the specific method of TSV formation and whether or not the OSAT has the capability. Economics, as always, also come into play.
But much of the TSV work currently being done in the chip industry is old hat to the MEMS industry. The concept involves middle-end-of-line (MEOL) processes done at OSATs. While some of the tools and processes involved are familiar from wafer level packaging methods, such as wafer bumping, TSV formation requires wafer etch, vapor deposition and some element of polish, and not just grinding, but chemical mechanical planarization (CMP). And regardless of the type of TSV implementation, they all involve exposing vertical copper vias.
“Four years ago, no one thought OSATs would do something in this area,” said Sesh Ramaswami, managing director of TSV and advanced packaging product development at equipment maker Applied Materials. “But for their own market growth and survival, they have to participate somewhere in the TSV adoption.”
And that’s meant a substantial investment for the handful of OSATs that endeavor to be players in TSVs, not to mention part of the aforementioned headache. A single TSV production line can cost somewhere in the vicinity of $30 million. CMP tools don’t come cheap.
Unless costs are recouped within the first couple of years, such an investment can become a financial burden, STATS ChipPAC’s Pendse said. As noted above, other than FPGAs and some high-end memory applications, the market for TSV applications hasn’t really blossomed in the current 2013 to 2014 time frame as many had originally predicted. But if OSATs want to be able to expose vertical copper vias in stacked/3D devices, it’s necessary. With MEOL processes, vias only 50 to 100 microns deep must be exposed in the backside of a wafer that’s approximately 750 microns thick.
“It has to be granular enough to expose these vias; it can’t just wipe them out,” Pendse said. Hence the use of CMP. “We’ve never used CMP in packaging before,” he added.
After this step, there is the handling of the thinned wafer, which in some cases needs to subsequently be metalized and wafer bumped, with temporary bonding and debonding processes. “That’s also new to us, handling the thin wafer,” Pendse said.
These steps also involve more stringent clean room requirements than what OSATs are used to.
So perhaps not surprisingly there are only a handful of OSATs that currently have this capability. Applied Materials has been working with several over the past few years, said Ramaswami. It’s required more than traditional tools sales and support that an IDM or foundry receives, what with the integration challenges. “Wafer thinning isn’t straightforward,” he said. “It requires some special knowledge.”
Furthermore, OSATs haven’t been able to rely on their customers, most of whom are naturally fabless chipmakers lacking the necessary in-house expertise. “How do we develop this capability? I’d say 50% we borrow from … in-house,” Pendse said, noting STATS ChipPAC’s expertise in fan out. The remainder has meant hiring people with expertise in the necessary areas.
Editor’s Note: As explained at length elsewhere on this site this is a news story written by me for another publication. This originally appeared on Semiconductor Engineering; it holds the copyright, of course.