Physical probing of devices using TSVs is proving a challenge to traditional test.
Among the challenges of a widespread adoption of 3D ICs is how to test them, particularly when it comes to through-silicon vias (TSVs). While not necessarily presenting a roadblock, TSVs use in the mainstream will almost certainly change traditional test strategies.
In fact for many chipmakers looking to stack their silicon, they may come to rely less on the traditional known good die (KGD) at final test and instead opt for so-called “probably good” die.
If one looks at the semiconductor industry as a whole, this issue of testing a device that relies on TSVs is nothing new. Compound semiconductors, such as image sensors, and MEMS have been utilizing TSVs for years. Furthermore, the problems with probing TSVs are not dissimilar to those introduced in years past with advanced packaging.
The use of delicate copper pillar bumps in flip-chip interconnects, for example, also has proven problematic in terms of physical contact during probing at final test. Physical contact can stress and ultimately damage the pillars. “Old-time spring contact probe doesn’t cut it anymore, ” said Gary Fleeman, vice president of marketing at Advantest Corp. “It’s becoming difficult to make contact. It is becoming quite challenging.”
So in a sense, the difficulties of testing devices with TSVs aren’t new. As with copper pillars, TSVs can be subject to damage with physical probing. But testing an image sensor and testing a stack of logic die, or something more complex—say a processor with memory—ultimately involve different challenges. “There are certain things that have been learned and can be leveraged,” said Mike Slessor, senior vice president and general manager of the MicroProbe Product Group at probe card maker FormFactor. But the devices are structurally very different, he added. It’s not a matter of simply taking the test strategy from one and applying it to the other.
Furthermore, in terms of stacking silicon, it’s one thing to have a single die with a damaged I/O; it’s something else to have a single damaged die that is part of a stack of several die, particularly if it renders the entire stack defective. At first glance that would seem to imply that 100% KGD are essential. However, as makers of high volume, mainstream semiconductor applications have begun to look to stacked die as a means of continuing device performance gains at advanced manufacturing nodes, in all likelihood it will mean new and different test strategies. Demanding 100% KGD may not prove economical in some cases, or even necessary.
But as with so many other aspects of mainstream 3D IC adoption, testing with TSVs is a question mark. “It creates a problem. How are you going to determine KGD?” said Mark Stromberg, semiconductor ATE analyst with Gartner Inc. “The industry is still kind of undecided how it’s going to address the problem,” he said.
Chipmakers are considering and evaluating several different test methodologies with regard to TSVs, Slessor said. In fact traditional physical probing of the device contacts—in this case, TSVs—hasn’t been completely dismissed. But it’s proving difficult, and the prevailing sentiment among MicroProbe’s customers is to avoid it. “We’ve done it, but it’s a challenge,” Slessor said, noting that this is the crux of the TSV/test debate. “If you don’t have to touch it, then you shouldn’t. The jury is still out on whether or not you have to.”
If not known good die, then what?
So if a chipmaker isn’t going to physically probe a device under test and drive current through it, that begs the obvious question: how to test said device? As Slessor said, the jury is still out, but as always, the answer ultimately will come down to cost—both test costs and device manufacturing costs.
Contactless probing would be a potential solution, but so far has proven problematic. “It hasn’t really developed. It isn’t progressing at all,” observed Advantest’s Fleeman.
The methods of contactless probing under consideration involve RF technology, but the physics involved with RF antennas are proving a limiting factor. The high frequencies and power densities of the electrical currents that mainstream semiconductors employ tend are proving a stumbling block to this method. “The tests require quite a bit more power than what can be generated,” MicroProbe’s Slessor said. “It’s something we continue to play around with,” he added, noting that there are inherent advantages to this approach, particularly as pitches shrink. But the technology won’t be ready anytime soon, he said.
BiST, or built-in self-test, is another option: building in extra structures within a device specifically for testing it. This adds complexity, to the manufacturing process, however, and thereby costs. Consequently it may not prove to be the best test strategy for low-cost, high volume device production when it comes to 3D ICs.
“Anything that adds significant potential costs is going to be a potential roadblock,” said Gartner’s Stromberg.
Another method under consideration is the use of specific test points: test or dummy pads placed among the TSVs themselves or on the outside of them that are used to contact and test the device. These can be fabricated in parallel with TSVs, adding relatively little in terms of manufacturing costs, Slessor said. Dummy pads can provide probe access to most of the structures in a device under test (hence the term “probably good die”). It also has the benefit of being familiar; it is an approach that DRAM manufacturers have employed for a long time.
Will known good die prove too expensive?
Whichever test strategy chipmakers adopt may depend on their specific application and the associated costs of fabrication and test. In other words, what proves most cost effective—determining probably good die vs. known good die? In some manufacturing scenarios, particularly among high-yield devices such as memory, it may prove cheaper to depend on a probably good die test strategy, even though it means some yield loss at final packaging, as the cost of that loss would still be less than than that of testing for 100% KGD prior to packaging.
This, of course, differs from tradition; wafer probe originally was designed to sort good die from bad die prior to packaging, sending 100 percent KGD off to be packaged.
“I don’t see it being a major roadblock to (widespread) 3D adoption,” said Slessor. “Instead of a roadblock, we’re looking at changes in test strategies.”
A lot depends on the combination of die involved in a 3D stack and the nature of the individual die along with what can and cannot be tested via dummy pads (or some other strategy alternative to physically probing TSVs). “Can they drive enough power through a device under test through dummy pads to get the results they want? That’s the question,” Slessor said, adding that there are related methods to infer the “goodness” of TSVs.
In terms of memory, this approach almost certainly will work, he said—with a combinations of a stacked processor and memory or stacked FPGAs it should work just fine in most cases. With 3D ICs involving high performance RF die, perhaps not.
In any event, the era of probably good die may be on the horizon.
Editor’s Note: As explained at length elsewhere on this site this is a news story written by me for another publication. This originally appeared on Semiconductor Engineering; it holds the copyright, of course.