Tales From The Silk Road

Duct tape and cheap electronics: the trials and tribulations of an expat.

Recently I wrote a two-part article on the impact low-cost quad-core and octo-core mobile processors are having on the mobile handset market here in Asia. In it I briefly mentioned that many travelers and expats in this part of the world—this part being Southeast Asia, generally speaking—come here, among myriad other reasons, for the cheap electronics available.

Semi EngineeringWhat prompted me to investigate and write the story is that I’m one of those expats. With the exception of seven months total spent on trips back at home in the States, I’ve lived for the past four years in either Viet Nam or Thailand. Before that I had traveled in both China and Japan. I could give you a lot of reasons why I chose to live here, but we’re talking about semiconductors and the products they go into, so we’ll stick to the topic of cheap electronics.

As I quickly discovered here, if I wanted name-brand, leading-edge devices or PC components, they aren’t so cheap after all. In fact sometimes, as in the case of Viet Nam, they are more expensive than what they would cost at home, thanks to import taxes. And that’s when I could even find that leading-edge stuff. I remember meeting an expat and hardcore PC gamer when I first came to Southeast Asia four years ago. (What are the odds of meeting a fellow Yankee nerd in a rural Thai town?) He used to make regular trips back to the States or to Hong Kong—not to visit friends or loved ones, but to buy leading-edge desktop components. At the the time, he lamented that you couldn’t even get the latest Intel quad-core processor in cosmopolitan Bangkok, and his gaming rig was a good six months behind those of his compatriots in other parts of the world.

Take my tablet…please

What does all this have to do with handsets in 2014, you ask? What about the cheap electronics? Don’t worry, I’m getting there. What I also quickly discovered about the cheap electronics that are available was that they were cheap for a reason. Take my first (of several) tablets that I bought here, here being Thailand (again, because they were cheaper than in Viet Nam, where I was living at the time).

No really, take it. You can have it.

I came to live abroad with my second-generation Kindle, which I absolutely loved, being a voracious reader (it’s a lot easier to travel with your library when your library consists of a few thousand files on a six-inch tablet with a battery that lasts for a week or two).

After years of use, however a couple of years ago my Kindle was really showing its age — duct tape was literally holding the housing together — and I thought I would try an Android tablet as a replacement. Plus, I thought that maybe an Android tablet would cut down on trips to the coffee shop with my laptop in tow.

Off to the electronics mall I went, while on holiday in Bangkok, and I came home to Sai Gon with a “Samsung” 9.7-inch Android tablet for the equivalent of about $100 — at the time, very cheap. Why was it cheap? Why is “Samsung” in quotation marks? Because it was a Chinese white-label device masquerading as a Samsung. It wasn’t even one of the better knockoffs; the firmware didn’t bother with a Samsung logo splash upon boot up, and the letters along the bottom of the screen proclaiming it a “Samsung” were cheap craft-store stick-on letters.

Yes, I knew before I bought it what it was. In fact, most vendors here are quite honest about the so-called “copies” they sell.

Anyway, fortunately for me it was fine for reading or surfing the Internet. Unfortunately, not both. It was equipped with a standard, 1 Gbyte ARM processor and a few gigs of RAM, but ask the device to do any sort of multitasking and it would choke, and choke badly (of course Android is probably a bit more bloated than it needs to be, but that’s a bit off topic). Open a dictionary while reading? Be prepared to wait a minute. Even after flashing it with a known third-party ROM version of Android, the multitasking performance, not to mention the battery life, was dismal. Watch a movie on it? Fine, as long as you didn’t have anything else running in the background and had the charger hooked up to it, too. Did I mention the battery life was nothing to brag about?

About this time, the slide-out keyboard on my beloved old Nokia had bit the dust, or rather the cable that connects the physical keyboard to the motherboard. The cost of replacing it more than covered the cost of a cheap handset here. So once more into the consumer breach, this time with a Chinese white-label Android phone; this time it had a dual-core ARM processor and 4 gigs of ram (for about $150 bucks).

The performance wasn’t brilliant (nor was the screen), but then it wasn’t bad, either; at least it could handle some light multitasking without bogging down; the screen remained responsive with more than one app running. A step in the right direction, but still it wasn’t really an alternative to a brand-name, leading edge device.

Let’s flash forward to several months ago. If traveling for a bit, or even just for an afternoon of work at a local cafe, I was tired of lugging around a laptop, a tablet and a phone. Whatever I could do on my tablet I could do on my phone, it’s true, but reading on that wee dim screen was not pleasant (and I tend to read for a couple of hours at a time, sometimes, on a slow afternoon or evening). Not to mention, I could kiss the battery goodbye after several chapters of Somerset Maugham.

I decided it was time to try a phablet, and once again I reasoned that I should buy one of the cheap knockoffs available here. It wasn’t because three times is a charm. It was to try out the phablet form factor. I figured then I would invest in the real-deal, if I liked it — namely a Samsung Note II. Long story short(er), I found a used Note I for cheap, and within a few weeks I was sold on the phablet, at least as far as Samsung was concerned — a screen large enough and with good enough resolution to make reading enjoyable, and a machine capable of multitasking without nary a lag. I also can get away with charging it once a day, even with several hours of reading thrown in, and it still fits in my pocket.

It’s probably only a matter of time until I trade it in for a new Note III (I’ve almost convinced myself that the improved battery life and the better image sensor are worth it).

But the knockoffs aren’t so knockoff anymore

While I began looking at phablets and phones with larger, four-plus-inch screens, I started noting the latest specs on the local brands and white-label devices with quad-core processors in them. Playing with these in the stores, and canvassing my Thai and expat friends who owned them, it became obvious that these second-tier handset and tablet makers had upped the game. This was thanks in large part to the availability of inexpensive quad-core mobile processors, namely from MediaTek.

The devices are responsive and more than capable of running several apps at once — say messaging, a browser, Facebook (and in lands where being social is a cultural staple, one can’t overlook the importance of social networking), not to mention making/receiving calls. Based on anecdotal evidence the image sensors in these devices are more than capable, as well.

It helps that these devices are literally hundreds of dollars cheaper than those of Apple, Samsung, HTC and Sony. Apple and Samsung still rule the roost here and elsewhere, in important markets like China — but as detailed in those two stories, that might not be the case for much longer.

Editor’s Note: As explained at length elsewhere on this site this is a news story written by me for another publication. This originally appeared on Semiconductor Engineering; it holds the copyright, of course.

Non-Visual Defect Inspection: The Tech of Tomorrow?

The chip industry is conservative when it comes to adopting new metrology and inspection. Will it ultimately see NVD inspection as a wunderkind, or an also-ran?

Remember when it first became obvious that the semiconductor manufacturing industry was going to expect lithography to resolve features smaller than the wavelength of light used in the litho tools themselves?

Semi EngineeringThanks to techniques such as the use of phase shift photomasks, sub-wavelength lithography is standard in chip fabs today. It might even be viewed as “old hat,” although still an expensive old hat.

Whether non-visual defect (NVD) inspection follows a similar trend remains to be seen. This is perhaps especially true in light of the history of metrology and inspection technology. Chipmakers always have been loathe to spend money on these often expensive tools and processes unless it proves indispensable in production. That explains why historical adoption rates of today’s standard metrology and inspection tools tend to have long ramps.

Still, it’s clear that as the industry begins to get serious about the forthcoming 14nm and 10nm nodes, NVDs, such as sub-monolayer residues and contaminants, have the potential to become increasingly problematic. One could argue they already are. But the key words here are non-visual and sub-monolayer, as in “sub-atomic.”

Chip manufacturing in the age of the electron

Generally speaking, device shrinks have proven problematic for years now. That’s nothing new and hasn’t been at least since R&D got underway for the 0.13-micron node. But things are getting really, really tiny now, not to mention complex—so much so that the industry is going to have to start worrying about specific electrons and Heisenberg.

“It hasn’t been uncommon with the 28nm and the 20nm transition where you get a device and everything looks great, but it doesn’t work right. You have, maybe for lack of a better term, a current flow problem,” said Dean Freeman, a semiconductor equipment analyst with Gartner Inc.

Freeman wasn’t talking about NVDs specifically, but commenting more generally on the challenges the industry faces at the 14nm and 10nm nodes and beyond, as the end of Moore’s Law creeps up on the horizon, along with exotic things like single-electron transistors.

The industry is probably going to see more problems like the one he described above, along with the need to be able to detect things that aren’t immediately understood. “We’re getting to the point where our modern measurements are getting past Heisenberg’s uncertainty principle,” Freeman said.

“One of the things people have to realize is, it’s just a lot more difficult to manufacture, even at sub-30nm, than people first thought,” said Bob Johnson, another analyst with Gartner who specializes in the metrology and defect inspection market segments. He noted that even a juggernaut such as Intel, with its deep pockets and advanced R&D efforts, was later than expected with its first sub-22nm chip.

In today’s advanced manufacturing fab line, a defect “can be something as subtle as something like two lines too close together that generate a certain amount of heat, which then throws off a timing circuit,” Johnson said.

As for NVDs, are they going to become more of a problem? Will the industry need NVD inspection tools on production lines, beyond the R&D and pilot lines? It’s too early to say just yet. Nevertheless there is some interesting and even compelling data out there.

So how do you see an NVD?

So if a defect is non-visual, i.e., you can’t see it because it doesn’t reflect or otherwise scatter light, how do you detect it? How do you “see” sub-monolayer contamination?

Currently there is only one company on the market offering NVD inspection tools to the chip industry: Qcept Technologies Inc. At the heart of Qcept’s tools is the concept of a vibrating Kelvin probe, a vibrating capacitor device that measures changes in the work function or potential in surface chemistry — without contacting the surface. Rather than vibrating a probe tip over a wafer surface, Qcept’s ChemetriQ scans the entire surface of a wafer, measuring differentials in work function. Its tools can scan a 300mm wafer in four minutes, according to the company.

Spun out of the Georgia Institute of Technology, the company announced its first beta site projects in 2011, one at a leading-edge logic fab and the other at a leading-edge memory fab; both involved inspection of 3X-nm production wafers. Since then it has placed systems at five of the top six chipmakers as determined by sales (not including fabless companies, naturally).

One of those chipmakers is South Korea’s Samsung Electronics. Samsung and Qcept published a joint paper earlier this year detailing the company’s use of Qcept’s ChemetriQ tool to identify a post-wet clean residue that was ultimately causing pitting defects in a later gate oxide process. The residue defect correlated with a known yield problem at end of line (EOL) test. Notably, while Samsung said it suspected the defect was occurring at the front-end of line gate module process, there was no matching defect pattern identified during optical inspection. The company used ChemetriQ inspection at several process steps in the gate and spacer module process, including post-gate lithography, post-gate etch and clean, post-spacer deposition and post-spacer etch and ash clean.

The resulting inspection data detected spots of increased work function in areas of the wafer that corresponded with the location of die failing at EOL test. Ultimately NVD inspection illustrated that the way a batch clean tool was handling the wafer was leaving unwanted residue on part of the wafer; among the most promising solutions was switching to a linear, single-wafer clean tool which enabled a more uniform post-clean surface and a significant yield increase at final test, according to Samsung.

Problems like the one discussed in the Samsung paper are not uncommon, according to Qcept. The company has had customers with 20 to 30 percent yield problems at end of line with no corresponding defect data, according to Robert Newcomb, executive vice president at Qcept. That’s where a lot of the time NVD inspection helps find the additional yield, when there is no corresponding optical defect inspection data, he said.

In October the company published a paper with Applied Materials Inc.’s Asia Product Development Center in Singapore and the Institute of Microelectronics in Singapore in which the companies used Qcept’s inspection technology to detect surface contamination within a chemical mechanical polarization (CMP) process used to reveal through-silicon vias (TSVs). The fact that Applied Materials turned to Qcept for CMP process development help perhaps speaks volumes, particularly given that Applied has its own optical defect inspection division — detecting NVDs is clearly a new thing.

While residues are one category of NVD, another is process-induced charge, according to Newcomb. “We have found that charge can result in yield failure and yield defectivity in many ways — electrostatic charge, discharge in the wafer — it can blow out the gate oxide fabbed three weeks ago,” he said. “Charge can result in electrochemical defects too.”

Charge problems tend to result from wet process steps, Newcomb noted. “Any process where you are doing a wet process to the surface of the wafer with different chemistries can result in these charge events,” he said. It is one area in which Qcept’s customers are focusing on in particular.

Wafer cleaning is incidentally one of the most common and repeated steps in a fab line. Some 200 steps can be involved with surface prep and cleaning with the fabrication of a complex device. Given the increasing use of exotic materials in semiconductor fabrication, that number is likely to grow at future nodes. “From that perspective, for wet cleans and surface prep, it’s more than just particles,” Newcomb said.

Future inspection tech or perfect future inspection tech?

Nevertheless, to say NVDs are a widespread phenomenon, or will be, or rather that NVD inspection is the wave of the inspection future — it’s too early to make that call. As Gartner’s Johnson noted, 30% yield problems at advanced nodes is hardly unusual. In fact some of the large complex die that appeared at 28nm node were rumored to have production yields in the 40% range.

Again, when it comes to metrology and inspection, chipmakers are loathe to spend money on the tools and add the steps in production. Any time there is a new metrology technology, it goes into the R&D area first before it gets adopted in production. Chipmakers have to be convinced that the problems illustrated in R&D are problems that are not just solved then and there, and instead must be monitored in production, Johnson said. And what if NVDs do prove a recurring problem in the production fab? “Then you would have to put some (NVD) inspection steps at critical points in the fab,” he said.

Johnson noted there have been promising metrology and inspection technologies in the past that failed to find their way into mainstream production, such as integrated metrology. In that case it proved too expensive and not absolutely necessary.

On the other hand, there is the example of optical critical dimension (CD) metrology technology. It had a long road to adoption. Like NVD inspection tech today, at the time optical CD inspection was a brand-new technology and it took the industry a while to figure out how to use it. Today, however, it’s an important part of the fab line and the metrology tool market.

As for NVD inspection technology and Qcept, time will tell. But it would seem that at least for the likes of Applied and Samsung, the evidence thus far is compelling.

Editor’s Note: As explained at length elsewhere on this site this is a news story written by me for another publication. This originally appeared on Semiconductor Engineering; it holds the copyright, of course.

Collaborate Or Go Home

Semiconductor architecture is easy. It’s the exotic materials that bring complexity, cost and the need to collaborate, not to mention new ways of doing business.

Technology is hard.

It’s no secret that it’s more difficult than ever to keep devices shrinking while increasing performance.

Semi EngineeringIt’s also old news that it is increasingly costly to be at the leading edge, as semiconductor production technology gets ever more complex — even as a maturing chip industry becomes ever more dependent on low-cost consumer devices.

But it has made for some strange developments in recent years, not the least of which has been IDMs moonlighting as foundries (and consequently Intel making Altera chips with ARM cores).

But it also has brought about a seemingly ever-increasing amount of cooperative research and development efforts throughout the supply chain — not to mention some odd bedfellows — and not just among chipmakers. The financial risk of gambling with technology and making the wrong choice has gotten so big that no one company can go it alone.

To a certain extent that’s due to natural maturation of the industry. But it is also largely because of the increasing complexity that’s become necessary to maintain device shrinks and performance gains. That complexity stems in part from the relatively odd architecture necessary at the leading edge now — metal gates and finFETs come to mind — but in large part stems from the materials necessary to make that odd architecture work.

We can’t just scale anymore

“Ten years ago you just scaled the device,” said Dean Freeman, an analyst and research vice president with Gartner Inc. “For 35 years we just used silicon, oxide and aluminum. That was it. Maybe a little silicon nitride. But we didn’t change the structure or focus of the transistor for 35 years. We changed the way we isolated it — shallow trench isolation — but the basic components and concepts were the same.”

Then, within the last 10 to 15 years, it became necessary to start making changes to the standard semiconductor materials set — that set of materials that hadn’t changed much in decades. Copper interconnects and low-k dielectrics came along about the turn of the century, and that was just the tip of the proverbial iceberg of complexity. After that it was time to tinker with the gates.

Today the industry has metal gates and the requisite high-k materials, strained silicon, finFETs, tunnel FETs, and 3DICs with through-silicon vias. Tomorrow it may be using heterogeneous CMOS devices: III/IV materials in transistor gates on a traditional silicon substrate.

Graphene transistors, anyone? Carbon nanotubes?

“You have this very rapid transition in a very short time frame using materials that we’re not that familiar with,” Freeman observed. While the use of germanium and gallium arsenide is hardly new, he noted, that has always been for other applications beyond the mainstream. “It’s still something new we’re putting into the transistor, and we have to look at parasitics, electron flow — how it all goes together. On top of that our interconnect keeps getting tougher to manage because our RC (resistance/capacitance) keeps going up.”

Generally speaking, it’s a problem spread all along the supply chain. Take wafer bonding and debonding, a key process in the formation of TSVs, for example. “This is certainly an area driven by increased complexity,” said Markus Wimplinger, corporate technology development and IP director of European-based chip equipment vendor EV Group (EVG).

It means that a company like EVG not only needs to work with its materials suppliers, but with its customers as well, gaining access to production volume data, data from conditions that can’t be reproduced in the lab. It’s perhaps a natural development, because more and more chipmakers are expecting their supply chains to take on more and more of the R&D burden.

Thus in this day and age, a lot of the collaboration, be it between companies and consortia, between companies and university partners, or directly between companies, is driven by the need to manage the learning curve so that each player can minimize the risk, not to mention the cost, involved in integrating a new solution to a technological problem.

“It is very important to integrate an optimized solution,” Wimplinger said. “That’s why we collaborate with customers and research institutes — we need access to that technology and data.”

It’s just too costly to try and go it alone anymore. By investing in R&D consortia, universities and collaborative programs with other companies, even competitors, the financial risk is spread and mitigated. Furthermore, with that approach, companies can investigate more than one potential option with a minimum of investment and risk, noted Robert Newcomb, executive vice president of non-visual defect inspection supplier Qcept Technolgies.

And the industry has learned that IP issues aren’t really a competitive issue when it comes to early R&D. As the industry saw with high-k gates and then with finFETs, a lot of that early learning that takes place involves so-called pre-competitive or non-competitive data. As Freeman observed, a transistor is a transistor is a transistor. “It’s how you integrate that transistor into your device, what you do with it, that’s what makes your product unique. How do you tweak that transistor and make it work faster than your competitor’s? I think we’re going to see more and more of that (pre-competitive) R&D, especially as we have fewer and fewer players,” he said.

Chipmakers aren’t the only ones working together for the common good
Another good example of what’s happening these days is the relationship between the aforementioned Qcept and Applied Materials. Applied Materials is the largest chip equipment vendor on the globe, and consequently is a big player in metrology and defect inspection. At first glance it might seem strange that it would work with another small defect inspection company — until one considers the type of defects Qcept finds: sub atomic monolayer defects, defects that don’t reflect light: non-visual defects (NVDs).

Applied has been heavily involved in backend packaging for 3D-ICs and related TSVs; the company’s Asia Product Development Centre has been working with the Institute of Microelectronics in Singapore to develop chemical mechanical planarization processes (CMP) to reveal TSVs. Copper contamination as result of the CMP process has subsequently been an issue with this approach.

AMAT recently presented the results of research it conducted with Qcept and the institute, however, which demonstrated that optimization of process conditions and chemistries can significantly lower wafer surface copper contamination from the CMP process. It used Qcept’s NVD inspection technology to characterize wafer surface contamination and consequently optimize the CMP process.

So here is a case of the largest chip equipment vendor in the world working with a research institute and a relatively small equipment vendor that began shipping production tools with its new inspection technology just a few years ago. “You are seeing a lot more company-to-company and company-to-university cooperation like this, as well as cooperative research with consortia,” Qcept’s Newcomb said, citing work on advanced packaging, advanced gate structures and the adoption of 450mm wafers.

“It’s interesting because you take all the logic guys, the foundries and the IDMs, and at some level they all compete for the same business,” he said. “But they realize to get to 450mm wafers, for example, they have to work together along with the equipment guys in order to achieve the most cost effective approach.”

Essentially competitors have to cooperate early on in order to be successfully competitive down the road. Thus a Goliath like Applied doesn’t hesitate to turn to a David like Qcept with unique technology to help solve what is at its core a materials integration problem.

Not just collaboration. New business models, too.

It would seem that the bar for startups is high in this market. Pre-competitive R&D is a necessity in part because the industry is maturing and there are fewer players left to deal with the complexity of the technology, and the costs involved are considerable, if not astronomical.

As Qcept has shown that in this late stage of CMOS development, however, there is still room for startups that can bring enabling technology. NVD inspection might not have been a necessity in the past, but it is proving so now.

Even this continually growing need for collaboration and cooperation itself is spawning new ways of doing business — and new businesses. Case in point is Intermolecular Inc. The company is nine years old and its business model is based on managing collaboration and the data that comes out of it. As the company states, its “partnership-based business model is most often implemented in collaborative development programs (CDPs), which focus on jointly solving specific technical problems.”

Dealing with those specific problems is what differentiates Intermolecular from research consortia such as Sematech or Europe’s IMEC, says Raj Jammy, senior vice president and general manager of the company’s semiconductor group. “They deal with solutions to complicated problems and how to apply them to the semiconductor supply chain, sharing them where it is directly applicable,” he said. “We help a company decide if a given solution is implementable and cost effective … we make sure the solution is aligned with their specific internal needs.”

Pre-competitive, collaborative research can generate a number of potential options for companies facing the same problem. As Gartner’s Freeman observed, the competitive trick lies in how you apply that data to a specific product. This is what Intermolecular specializes in, Jammy said.

“Which billion dollar option should I bet on? Today’s companies need to know that,” he said. “They are taking risks, working towards making that solution the best that they can.” In short, companies need what EVG’s Wimplinger characterized above as that “optimized solution.”

Take the example of the exotic materials often in use in fabs today. Typically what has happened previously is that research consortia have developed a class of materials that address a given problem. “Once you have a class of materials, a company can identify a solution; each company must decide which specific material it needs, how to incorporate it into product designs and production flows,” Jammy said; this is where his company comes in.

Is Intermolecular’s business model one that would have existed within the chip industry in years past? Even a decade ago?

“It would have had a very different context in the 1990s; what the company would be doing would be different back then,” Jammy said. Just 15 years ago, the industry didn’t have to deal with the plethora of materials employed to make leading edge semiconductor tech work. “That problem has become much more complex and acute of late,” Jammy said.

Editor’s Note: As explained at length elsewhere on this site this is a news story written by me for another publication. This originally appeared on Semiconductor Engineering; it holds the copyright, of course.

ATE Market Changes With The Times

A consumer-device driven chip industry drives demand for more known good die and quick time to market.

A declining PC market in recent years coupled with the continuing growth of mobile phones and tablets has meant changes throughout the semiconductor supply chain, and automated test equipment is no exception.

Semi EngineeringFor example, a decade ago memory test—namely DRAM—was a large market compared with that of nascent system-on-a-chip (SoC) testing. In fact, at the time some test executives questioned the marketing hubub over SoCs. Of course the PC was still king at the time, even in a post-dotcom bubble world. Smartphones were still expensive and uncommon outside the business world while tablet computers were a rarity (and still thick and heavy).

By 2008 the SoC test market and the memory test market were essentially the same size, however, as the market for consumer devices continued to grow, led by handset growth.

In the ensuing years SoC test continued to outgrow memory test. Last year in 2012 the memory test market was $362 million, while the SoC test market was $1.7 billion, according to Mark Stromberg, a semiconductor ATE analyst with Gartner Inc. The company forecasts that the SoC test market will continue to outstrip that of memory: the memory market will hit $620 million by 2017, while the SoC test market will reach $2.85 billion. In fact at an annual growth rate of 2.5 to 3 percent between 2012 and 2017, the SoC test market is set to slightly outpace the overall market growth for semiconductor ATE.

Worldwide Shipments by Device

While the overall memory test market may be declining in terms of annual growth, the use of NAND flash in all those phones and tablets has driven an increase in demand for NAND ATE. “NAND testers have really kind of accelerated nicely,” said Stromberg. “It’s a really strong market this year.”

As the markets for test have changed, so have the players. Like elsewhere in the semiconductor supply chain, today there are considerably fewer than there were a decade ago, as exits or mergers have reduced their numbers.

Viewed in terms of sales there are two major semiconductor ATE vendors, Advantest Corp. and Teradyne Inc., with LTX-Credence a distant third. Advantest, incidentally, completed its merger with Verigy (itself the former semiconductor test business previously spun out from Agilent Technologies) a year and a half ago; it debuted its first product developed since that merger last month at Semicon West, the T5831. Not surprisingly, Advantest is billing the T5831 as an advanced NAND tester, among its capabilities.

No Time to Lose

Of course some things never change. Cost-of-test, time-to-yield and time-to-market remain primary drivers, and likely always will for ATE. Each generation of tester seems to be able to test more devices in parallel than the previous generation. Today memory testers can test some 1,000 devices in parallel, while non-memory ATE and probe cards have evolved to test as many as 16 to 32 devices in parallel.

But mobile devices, which have given rise to the prevalence of not just SoCs and NAND flash but multi-chip modules and packages, are providing new challenges and drivers for ATE companies.

“The thing we are seeing becoming more important over the last two years is that our customers who are dealing with (their) Tier 1 customers, large handset manufacturers and computer manufacturers are beginning to institute really strict quality standards,” said Greg Smith, computing and communications business unit manager at Teradyne.

These customers are striving for extremely low defective parts per million (DPPM) levels, namely because these consumer driven markets move and react extremely fast. Customers playing in mobile consumer end markets often want to move from sample devices into volume production within the span of one quarter—just three months, noted Gary Fleeman, vice president of marketing at Advantest.

The fact that end markets react quickly is a factor, as well. Take for example the introduction of a new name-brand flagship mobile phone, such as a Samsung Galaxy or Apple iPhone, which will sell 100 million units within a few months of first hitting the market. Even with a relatively low DPPM of 100, that translates into 10,000 customers, observed Smith. Those customers will spread the news of their faulty device via the Internet and social networks.

“Because of how connected the world is, you can end up with these relatively low-rate problems becoming a big reputation problem,” he said, citing Apple’s notorious iPhone antenna issue. “All of these suppliers to Tier 1 developers of smartphones and tablets understand the asymmetric risk of a quality problem.” Thus those concerns filter down to ATE suppliers.

This pressure for low defectivity in a timely manner is a particularly peculiar issue, perhaps, for ATE vendors when dealing with NAND flash. Ubiquitous NAND devices have become so dense and complex, and manufacturing turnaround times so fast, that it’s virtually impossible to fabricate a perfect NAND device. It’s up to the related device controller to manage the errors.

This can lead to an unwanted increase in test times, said Ira Leventhal, senior director of R&D for Advantest’s Americas Memory unit. In response to this problem, the company designed its new tester, the T5831, to provide error-related analysis in the background while the device is in operation under test. The tester also features a real-time source-synchronous interface in which the device under test provides timing clock data to the tester while it is itself being tested.

Interconnects and stacked devices

While managing the ever-present time-to-market and test cost issues, ATE vendors also have to have a care for the near future. Current multi-chip modules and packages and stacked packages or 3D packaging are keeping ATE vendors on their toes. “This is the age of interconnect,” observed Advantest’s Fleeman. “Even conservative businesses like automotive (electronics) are moving into multi-chip packaging and multi-chip dies.”

While packages have gotten more complex and interconnects more dense, the end products they are going into keep getting smaller and thinner, which means the packages have to be thinner as well, and consequently more delicate. “It’s changing the handling environment,” Fleeman said. “Handlers aren’t sexy, they’re utilitarian, but we have to think about it,” he added. Thermal issues are also more prevalent than ever, thanks to more powerful devices in ever-thinner packages.

The need for dense interconnects coupled with the use of corresponding technologies such as copper micropillars are bringing further challenges, particularly for probe card makers. “Companies like Amkor are doing a good job of bringing dense contacts to the industry,” Fleeman said, noting a single device may contain some 10,000 to 20,000 delicate copper micropillars. “Contact is becoming quite challenging.”

Through-silicon vias (TSV) and 3D ICs are another potential headache for ATE vendors. “We’ve spent a fair amount of time thinking about it, but it is still very much up in the air,” said Teradyne’s Smith.

The attraction of TSV and 3D methodologies are the potential to create a device that contains stacked memory on top of a mobile processor, for example. Such a device would provide memory with lower power requirements yet larger bandwidth than what is possible today. “That’s the Holy Grail. That’s what people have been trying to achieve,” said Smith. While no one has achieved such a device just yet, the efforts have nevertheless driven a lot of innovation among memory makers.

And anytime you stack assemblies of devices before they are packaged together, the testing of said devices naturally gets complex. This is driving more test to be done at the wafer level to ensure the devices going into those assemblies and packages are good. The potential problem with multi-chip devices is that if one chip is bad, the entire device is bad. It’s also driving the expanded use of such test methods as boundary scan and built-in self test (BIST), which will require ATE to support such methods.

Then there is the need to test such a completed device or module as a system. “Imagine you have a baseband processor, RF chip, a power management chip, and some memory, and it’s all stacked into this complex 3D IC,” said Smith. “The best way to ensure quality is to perform all of those functions involved on all of the die at the same time, the equivalent of placing a call, browsing the Web, or sending a text message. It’s driven us to add features to our testers to communicate in the protocols of the devices in real time. We’ve developed our current generation of testers to handle this type of stuff.”

It’s still relatively specialized, and consequently small parts of the market that utilizes TSV and 3D ICs, such as MEMS and certain image sensors. But as for highly complex digital devices using these technologies, “We’re still waiting for that to emerge as a real factor,” Smith said.

Editor’s Note: As explained at length elsewhere on this site this is a news story written by me for another publication. This originally appeared on Semiconductor Engineering; it holds the copyright, of course.

High NA EUV Litho May Require Larger Photomask Size

In the meantime, will the mask supply chain have six-inch EUV masks ready by 2015?

With extreme ultraviolet lithography (EUV) potentially being used in pilot production in a few years, it raises the question of larger photomasks sizes—will the industry need them, and if so, when?

Semi EngineeringWhile there has been discussion of late about the possible need to transition to a larger mask size, veterans of the mask business may feel it’s déjà vu all over again. Back in the mid 1990s there was much discussion about transitioning from six-inch to nine-inch masks—so much so that standards were written. Then, as now, the transition (or more accurately, the lack of one) had to do with economics and the choice of lithography technologies used in semiconductor manufacturing.

The forthcoming choice today involves EUV, and as always when the discussion involves EUV, to answer these questions involves a combination of extrapolation and hypothesis. But the industry is finally getting close to putting EUV tools in fabs.

ASML suggested just last week that it is on track to deliver a throughput of 70 wafers per hour (wph) on its first production EUV lithography tool, the NXE:3300B, sometime next year. Ostensibly that will be with an 80 watt power supply, improving on the source in its current development tool, the NXE:3100, which currently can sustain 50 watts over long periods of time, according to the litho tool vendor.

If this holds true, the chip industry could see EUV exposure tools and pilot lines in chipmakers’ fabs within a few years’ time, although the throughput will have to continue to improve for it to move into mainstream production. The current consensus is that widespread use of EUV— assuming current estimates of power source improvements hold true—won’t happen until the end of the decade and beyond at the 10nm and 7nm nodes.

So in terms of the mask industry, it could be looking at a size transition around the 2018 to 2020 time frame. But worrying about that may be putting the cart before the horse, cautions Stefan Wurm, director of lithography for Sematech. “The industry needs to make the decision on doing high NA or not, and if it proves the right choice, it’s got to be a high NA solution that shares multiple nodes,” he said. While the question of high NA EUV is coupled with the need for a larger mask size, “it’s not something that will be decided tomorrow.”

Of more pressing concern is the availability of six-inch EUV photomasks in the 2015 time frame for those pilot lines, Wurm said. “The goal is very simple: make sure there is an adequate supply that supports the yield requirements for EUV ramp up.”

In fact, mask availability is of more concern than source power at this point, he said. Chipmakers are making a huge effort with regard to supporting lithography vendors on EUV source development to ensure success, he noted. Intel’s investment in ASML is a primary example.

“On the mask side it’s a little different because you have to look at the whole supply chain,” Wurm said. While suppliers are waiting to see the outcome of source development, it begs the question: Will they have time and resources to catch up once the source power is there? “We’re more concerned about the mask blanks supply chain than we’re concerned about the source,” he added.

There are still a number of technical issues to address if six-inch EUV masks are going to be ready for pilot production in a few years. “Everything that’s related to yield and masks and mask lifetime and blank defectivity is certainly at the center of that,” Wurm said.

Why larger photomasks?

Even with the adoption of EUV there aren’t necessarily economic or technical reasons for the industry to move to a larger mask size, or at least not right away. It depends largely on which way the industry goes to get to the resolution needed at the 10nm node and beyond, whether it adopts some sort of double patterning scheme with EUV or opts for a higher numerical aperture (NA) EUV exposure technology.

Increasing the NA—seen as necessary if the industry is going to avoid double pattering—will mean increasing the magnification of EUV exposure tools, which means a smaller exposure field size and consequently more exposures (and less throughput), unless a larger mask size is used.

Throughput, and thereby economics, is the key part of the equation. Based on the technical papers presented at SPIE and elsewhere in recent years, it appear the techniques used to achieve the higher NA would cut throughput by as much as 50%. This can be alleviated somewhat with a larger mask size, noted Franklin Kalk, CTO of Toppan Photomasks.

“It’s interesting because the mask size can help the throughput, but it doesn’t bring it back to where it was,” he said.

Furthermore, it all comes back to EUV source power as well. “If we increase the mask size, it won’t improve the throughput without the (EUV source) power,” said Banqui Wu, Applied Materials’ CTO for its photomask etch products business. “People assume we have the power. If we get the power, we can improve both the resolution and the throughput.”

But what about bigger wafers, too?

As Kalk and Wu suggest, if the source power doesn’t continue to scale as hoped, even if EUV is put into production there would be little need for a larger mask size because high NA EUV wouldn’t be feasible without the requisite source power. But, as Sematech’s Wurm notes, if the source power isn’t available for high NA EUV at the end of the decade, it probably will mean that EUV never made it into production in the first place, and thus it will become a moot point.

Even if high NA EUV proves viable, the smaller exposure field possibly could prove beneficial with high NA EUV at the 10nm and 7nm node, in spite of the extra steps and lower throughput that would result. Yield and defect control conceivably would be easier to manage with the smaller exposure field, Wu noted.

Wrapped up in the argument for larger mask sizes is the transition from 300mm wafers to 450mm wafers, although the wafer size transition wouldn’t necessarily require larger mask sizes, just as the migration from 200mm to 300mm wafers did not. “If the industry doesn’t adopt EUV for production, or it is used on a very limited basis, it seems unlikely the industry would opt to migrate to a larger mask size,” Kalk said. “In principal, on 450mm (wafers), it doesn’t really require a larger mask.”

Applied’s Wu said that a larger mask size in combination with 450mm wafers could provide benefits in terms of wafer etch and chemical-mechanical planarization (CMP). However in terms of throughput, in and of itself a larger mask size wouldn’t really result in any improvements without the adoption of EUV, regardless of wafer size, he said.

Bigger mask size means bigger—much bigger—CapEx

So if high NA EUV is ready for the 10nm node, a transition to a larger mask size, likely nine-inch masks, seems likely. Will the industry be ready? That will remain to be seen, but one thing everyone can agree on: It will require considerable capital investment cycle.

“We’re always used to scaling equipment; we’ve been doing it since the three-inch (mask) days,” said Amitabh Sabharwal, general manager for photomask etch products at Applied. “If there is significant pull and there is an industry demand, we can do it.”

But a transition won’t be cheap.

“The bottom line is it’s going to cost a lot of money to do it,” said Toppan’s Kalk. “We haven’t done a thorough analysis of a nine-inch EUV mask (manufacturing) line or 12-inch EUV capable mask line, but it has to be approximately 200 million,” he said – roughly half the cost of a leading edge manufacturing line today producing photomasks for 28nm manufacturing.

It could mean changes in the photomask supply chain as well. While the big three semiconductor photomask suppliers—Toppan, Photronics and Dai Nippon—have kept their hands in the leading edge by partnering with large IDMs, the pool of those playing at the leading edge dwindles with each technology node. With only a handful of companies likely to be developing chips at the 10nm node, and the considerable capital expense involved, further consolidation among merchant mask suppliers could be in the offing in the years ahead.

Furthermore, with only a small number of chipmakers producing chips at the 10nm node there may not be enough tools sold to justify having two or more suppliers for each piece of equipment. For example, “we’re not going to find multiple providers of writers or etchers,” Kalk said. “I just don’t think that’s going to happen.”

Aside from the economic issues, there will be many technical issues to address when it comes to migrating to a larger mask size along with EUV, such as critical dimension (CD) resolution and mask metrology and defectivity. This is not to mention the technical hurdles that still exist for six-inch EUV masks.

There also is the question of using nine-inch mask sets with six-inch mask sets. While at first glance it may seem plausible to continue to use six-inch mask sets for non-critical layers even as nine-inch masks are used for critical layers, thereby saving costs, this method would introduce its own technical hurdles, such as alignment.

EUV mask availability—be it six-inch or later nine-inch masks—is perhaps indicative of a larger phenomenon in the chip industry beyond EUV and photomasks. “The health of the supply chain in general, not just on the mask side, will need more attention in the industry,” said Wurm. The costs for equipment and materials vendors continues to increase, and their capability to support R&D doesn’t always keep track with what the industry requires of them.

“That’s something the industry needs to keep in mind,” he said. “How can we work together to make sure we have a healthy supply chain in all areas?”

Editor’s Note: As explained at length elsewhere on this site this is a news story written by me for another publication. This originally appeared on Semiconductor Engineering; it holds the copyright, of course.