While compound semis have used TSVs for years, hurdles remain for adoption in high-volume memory and logic apps.
One issue with the adoption of TSVs in 3D ICs in mainstream semiconductor applications revolves around the throughput of the temporary wafer bonding and debonding process. This doesn’t necessarily equate to a roadblock, but work certainly remains to be done on this and related issues.
On one hand, TSVs already are being used in the manufacturing of compound semiconductors and MEMS, and have been for a decade or so. Many of the image sensors used in current consumer devices, for example, employ 3D ICs, and these are being produced in high volume.
In fact, in some products in production today, TSVs have enabled better products, noted Thorsten Matthias, business development director at bonding equipment vendor EV Group (EVG). In the case of image sensors, using TSVs have enabled sensors that produce a better quality image or sensors that produce an image faster. “Even in some of the cheapest devices, TSVs have been implemented where it makes sense,” Matthias said.
But if one is talking about memory and logic for consumer devices, there are reasons the forecast adoption of TSVs has been pushed out. Before TSVs in stacked silicon are utilized in production there are still a few hurdles to be crossed. One of the issues is throughput of the temporary bonding and debonding process. Another significant hurdle for the mainstreaming of TSVs involves wafer-level testing.
“The throughputs on that process are still pretty low,” said Mark Stromberg, an analyst with Gartner Inc. Current systems on the market can manage throughputs of 20 to 25 wafers per hour. Compared to other fab-line tools with a typical throughput of some 60 wafers per hour, that’s a bottleneck in terms of high volume production. “This is one of the reasons TSVs haven’t taken off, especially in the current market conditions,” Stromberg said.
Theoretically, one could add more than one bonding/debonding tool to the flow, but at a cost of several million dollars or more per tool, that is an expensive proposition. However as with other fab tools, bonding and debonding equipment vendors have added multiple chambers to tools to improve throughput (as well as accommodating various and differing bonding and debonding process flows). Austria-based EV Group, for example, unveiled its EVG850 temporary bonding and debonding (TB/DB) tool last year. Built on the company’s XT Frame platform, the EVG850TB/DB can accommodate up to nine process modules, doubling the process capacity of EVG’s previous temporary bonding and debonding tools.
Performance gains vs. cost gains
Still, there is work to be done before the advent of temporary wafer bonding and debonding in TSV fabrication in the production of memory and logic, and not just in terms of throughput. There are a number of process flows that have the potential to be extended to memory production, Matthias said. Even so, when it comes to high volume production of these devices, the industry is looking at a steep learning curve, moving from, say, thousands of wafers in a production run of compound semiconductors, to the tens of thousands of wafers involved in the production run of memory and logic destined for consumer devices such as mobile phones.
“In terms of design, it can be quite challenging,” Matthias observed, referring to the question of whether or not to implement TSVs in such a production environment.
“But I would say the industry has moved beyond the feasibility study phase and is now in the reliability and infrastructure phase,” suggested Matthias’ colleague, Thomas Uhrmann, also business development manager at EV Group. This is particularly true in terms of the throughput question, Uhrmann said, acknowledging that this is a critical issue in terms of a wider adoption of TSVs.
But it’s not just a matter of improving throughput only. Multiple modules on a temporary bonding and debonding tool are also important for accommodating differing steps and process flows. Another challenge in this process has been the use of adhesives to bond a thin device wafer to a temporary carrier wafer so it can go through the back thinning and other process steps required in TSV formation.
The thermal characteristics of some adhesives used in the process are such that they can’t survive in the high temperatures of the chemical vapor deposition (CVD) and physical vapor deposition (PVD) processes typically used in the manufacturing of memory and logic devices. There is much work being done within the industry at the moment to improve the thermal stability of adhesives used in the temporary bonding process, while some companies have implemented low temperature CVD/PVD processes that are compatible with the adhesives, Uhrmann said.
“We’re still working on it, the ability to withstand the higher temperatures,” he said. “It’s an ongoing process.”
With logic and memory chipmakers planning definitively—or at least mulling over—the implementation of TSVs in production within two to three years, the type of bonding/debonding used may depend on the specific device involved and the related production costs. Some devices require high process temperatures, and there are some adhesives in production today that can withstand those higher temperatures, Matthias said. There are related practical reasons in terms of production to maintain a process flow with higher process flows, Uhrmann suggested, although these are somewhat less necessary so than they were three to five years ago.
Furthermore, being able to process at lower temperatures provides additional flexibility in terms of process flows, and most mainstream chipmakers are looking at bonding and debonding processes coupled with CVD/PVD processes in the range of 200 to 320 degrees, Matthias said.
Uhrmann suggested that while there is still a learning process ahead for the industry when it comes to bonding and debonding and TSV production, as more wafers are processed and more statistical data is gathered, improvements can be made in terms of integration with upstream and downstream production flows. “This will allow us to optimize the temporary bonding and debonding process flow,” he said.
As Matthias summed it up: “It’s very challenging and interesting to work in this field.”
Editor’s Note: As explained at length elsewhere on this site this is a news story written by me for another publication. This originally appeared on Semiconductor Engineering; it holds the copyright, of course.