Semiconductor architecture is easy. It’s the exotic materials that bring complexity, cost and the need to collaborate, not to mention new ways of doing business.
Technology is hard.
It’s no secret that it’s more difficult than ever to keep devices shrinking while increasing performance.
It’s also old news that it is increasingly costly to be at the leading edge, as semiconductor production technology gets ever more complex — even as a maturing chip industry becomes ever more dependent on low-cost consumer devices.
But it has made for some strange developments in recent years, not the least of which has been IDMs moonlighting as foundries (and consequently Intel making Altera chips with ARM cores).
But it also has brought about a seemingly ever-increasing amount of cooperative research and development efforts throughout the supply chain — not to mention some odd bedfellows — and not just among chipmakers. The financial risk of gambling with technology and making the wrong choice has gotten so big that no one company can go it alone.
To a certain extent that’s due to natural maturation of the industry. But it is also largely because of the increasing complexity that’s become necessary to maintain device shrinks and performance gains. That complexity stems in part from the relatively odd architecture necessary at the leading edge now — metal gates and finFETs come to mind — but in large part stems from the materials necessary to make that odd architecture work.
We can’t just scale anymore
“Ten years ago you just scaled the device,” said Dean Freeman, an analyst and research vice president with Gartner Inc. “For 35 years we just used silicon, oxide and aluminum. That was it. Maybe a little silicon nitride. But we didn’t change the structure or focus of the transistor for 35 years. We changed the way we isolated it — shallow trench isolation — but the basic components and concepts were the same.”
Then, within the last 10 to 15 years, it became necessary to start making changes to the standard semiconductor materials set — that set of materials that hadn’t changed much in decades. Copper interconnects and low-k dielectrics came along about the turn of the century, and that was just the tip of the proverbial iceberg of complexity. After that it was time to tinker with the gates.
Today the industry has metal gates and the requisite high-k materials, strained silicon, finFETs, tunnel FETs, and 3DICs with through-silicon vias. Tomorrow it may be using heterogeneous CMOS devices: III/IV materials in transistor gates on a traditional silicon substrate.
Graphene transistors, anyone? Carbon nanotubes?
“You have this very rapid transition in a very short time frame using materials that we’re not that familiar with,” Freeman observed. While the use of germanium and gallium arsenide is hardly new, he noted, that has always been for other applications beyond the mainstream. “It’s still something new we’re putting into the transistor, and we have to look at parasitics, electron flow — how it all goes together. On top of that our interconnect keeps getting tougher to manage because our RC (resistance/capacitance) keeps going up.”
Generally speaking, it’s a problem spread all along the supply chain. Take wafer bonding and debonding, a key process in the formation of TSVs, for example. “This is certainly an area driven by increased complexity,” said Markus Wimplinger, corporate technology development and IP director of European-based chip equipment vendor EV Group (EVG).
It means that a company like EVG not only needs to work with its materials suppliers, but with its customers as well, gaining access to production volume data, data from conditions that can’t be reproduced in the lab. It’s perhaps a natural development, because more and more chipmakers are expecting their supply chains to take on more and more of the R&D burden.
Thus in this day and age, a lot of the collaboration, be it between companies and consortia, between companies and university partners, or directly between companies, is driven by the need to manage the learning curve so that each player can minimize the risk, not to mention the cost, involved in integrating a new solution to a technological problem.
“It is very important to integrate an optimized solution,” Wimplinger said. “That’s why we collaborate with customers and research institutes — we need access to that technology and data.”
It’s just too costly to try and go it alone anymore. By investing in R&D consortia, universities and collaborative programs with other companies, even competitors, the financial risk is spread and mitigated. Furthermore, with that approach, companies can investigate more than one potential option with a minimum of investment and risk, noted Robert Newcomb, executive vice president of non-visual defect inspection supplier Qcept Technolgies.
And the industry has learned that IP issues aren’t really a competitive issue when it comes to early R&D. As the industry saw with high-k gates and then with finFETs, a lot of that early learning that takes place involves so-called pre-competitive or non-competitive data. As Freeman observed, a transistor is a transistor is a transistor. “It’s how you integrate that transistor into your device, what you do with it, that’s what makes your product unique. How do you tweak that transistor and make it work faster than your competitor’s? I think we’re going to see more and more of that (pre-competitive) R&D, especially as we have fewer and fewer players,” he said.
Chipmakers aren’t the only ones working together for the common good
Another good example of what’s happening these days is the relationship between the aforementioned Qcept and Applied Materials. Applied Materials is the largest chip equipment vendor on the globe, and consequently is a big player in metrology and defect inspection. At first glance it might seem strange that it would work with another small defect inspection company — until one considers the type of defects Qcept finds: sub atomic monolayer defects, defects that don’t reflect light: non-visual defects (NVDs).
Applied has been heavily involved in backend packaging for 3D-ICs and related TSVs; the company’s Asia Product Development Centre has been working with the Institute of Microelectronics in Singapore to develop chemical mechanical planarization processes (CMP) to reveal TSVs. Copper contamination as result of the CMP process has subsequently been an issue with this approach.
AMAT recently presented the results of research it conducted with Qcept and the institute, however, which demonstrated that optimization of process conditions and chemistries can significantly lower wafer surface copper contamination from the CMP process. It used Qcept’s NVD inspection technology to characterize wafer surface contamination and consequently optimize the CMP process.
So here is a case of the largest chip equipment vendor in the world working with a research institute and a relatively small equipment vendor that began shipping production tools with its new inspection technology just a few years ago. “You are seeing a lot more company-to-company and company-to-university cooperation like this, as well as cooperative research with consortia,” Qcept’s Newcomb said, citing work on advanced packaging, advanced gate structures and the adoption of 450mm wafers.
“It’s interesting because you take all the logic guys, the foundries and the IDMs, and at some level they all compete for the same business,” he said. “But they realize to get to 450mm wafers, for example, they have to work together along with the equipment guys in order to achieve the most cost effective approach.”
Essentially competitors have to cooperate early on in order to be successfully competitive down the road. Thus a Goliath like Applied doesn’t hesitate to turn to a David like Qcept with unique technology to help solve what is at its core a materials integration problem.
Not just collaboration. New business models, too.
It would seem that the bar for startups is high in this market. Pre-competitive R&D is a necessity in part because the industry is maturing and there are fewer players left to deal with the complexity of the technology, and the costs involved are considerable, if not astronomical.
As Qcept has shown that in this late stage of CMOS development, however, there is still room for startups that can bring enabling technology. NVD inspection might not have been a necessity in the past, but it is proving so now.
Even this continually growing need for collaboration and cooperation itself is spawning new ways of doing business — and new businesses. Case in point is Intermolecular Inc. The company is nine years old and its business model is based on managing collaboration and the data that comes out of it. As the company states, its “partnership-based business model is most often implemented in collaborative development programs (CDPs), which focus on jointly solving specific technical problems.”
Dealing with those specific problems is what differentiates Intermolecular from research consortia such as Sematech or Europe’s IMEC, says Raj Jammy, senior vice president and general manager of the company’s semiconductor group. “They deal with solutions to complicated problems and how to apply them to the semiconductor supply chain, sharing them where it is directly applicable,” he said. “We help a company decide if a given solution is implementable and cost effective … we make sure the solution is aligned with their specific internal needs.”
Pre-competitive, collaborative research can generate a number of potential options for companies facing the same problem. As Gartner’s Freeman observed, the competitive trick lies in how you apply that data to a specific product. This is what Intermolecular specializes in, Jammy said.
“Which billion dollar option should I bet on? Today’s companies need to know that,” he said. “They are taking risks, working towards making that solution the best that they can.” In short, companies need what EVG’s Wimplinger characterized above as that “optimized solution.”
Take the example of the exotic materials often in use in fabs today. Typically what has happened previously is that research consortia have developed a class of materials that address a given problem. “Once you have a class of materials, a company can identify a solution; each company must decide which specific material it needs, how to incorporate it into product designs and production flows,” Jammy said; this is where his company comes in.
Is Intermolecular’s business model one that would have existed within the chip industry in years past? Even a decade ago?
“It would have had a very different context in the 1990s; what the company would be doing would be different back then,” Jammy said. Just 15 years ago, the industry didn’t have to deal with the plethora of materials employed to make leading edge semiconductor tech work. “That problem has become much more complex and acute of late,” Jammy said.
Editor’s Note: As explained at length elsewhere on this site this is a news story written by me for another publication. This originally appeared on Semiconductor Engineering; it holds the copyright, of course.